1. Field of the Invention
This invention relates generally to terminal systems and more particularly to display systems with apparatus for generating a Direct Memory Access priority system.
2. Description of the Prior Art
Terminal systems having a central processor (CPU), a memory subsystem and a number of peripherals are well-known. One method of controlling the system is by having the CPU, under program operation, control the peripheral input/output communication with memory through the CPU. This type of operation is satisfactory for low speed peripheral or for dedicated applications. This type of operation is not satisfactory for peripherals with high speed input/output requirements with memory.
To solve this problem, the prior art had designed systems whereby the high performance peripherals communicated with memory without the intervention of the CPU. The CPU communicated with memory on CPU cycles and the peripherals communicated with memory during Direct Memory Access (DMA) cycles with the peripherals stealing CPU cycles to communicate with memory. This system had the disadvantage of reducing system throughput in an application whereby the high performance peripheral prevented CPU cycles.
To solve this problem, systems with dedicated CPU channels and DMA channels were designed. This had the problem that peripheral I/O throughput could be reduced by having high priority peripherals hogging the DMA cycles thereby preventing low priority peripherals from accessing memory. This problem is somewhat alleviated by the invention of U.S. Pat. No. 3,553,656 by D. E. Bernhardt, entitled "Selector for the Dynamic Assignment of a Priority on a Periodic Basis," wherein user devices are selectively assigned highest priority depending upon the last device granted access. This, however, still has the problem of the device assigned highest priority hogging the memory bus.
These problems were eased somewhat by the system described in an article from Computer Design, January, 1978, pages 117-124, by Joseph Nissam, entitled "DMA Controller Capitalizes on Clock Cycles to Bypass CPU". A system is described having CPU cycles and DMA cycles. CPU cycles are stolen by the DMA devices; however, the CPU can interrupt the DMA cycle.
Also, a DMA controller has eight DMA request/acknowledge lines to provide bidirectional control between the peripherals and the DMA controller. Each DMA line has a fixed priority. Each channel has a register to store the data length of the peripheral accessing the channel. The device relinquishes the channel when (a) the register has counted down to zero, (b) a request from a peripheral on a higher priority channel is received by the DMA controller, or (c) the CPU requests a CPU cycle.
This solution requires considerable DMA logic and "housekeeping", and retains some of the reduced throughput problems of the CPU cycle stealing systems discussed above and still has the problem of high priority peripherals hogging the bus.